1. Field of the Invention
The present invention relates to design process for a semiconductor integrated circuit and in particular to a semiconductor integrated circuit design tool, a computer implemented method for designing a semiconductor integrated circuit, and a method for manufacturing a semiconductor integrated circuit.
2. Description of the Related Art
In a manufacturing process of a semiconductor integrated circuit, unifying electrical characteristics of a plurality of transistors is a crucial factor to improve the defect rate. To unify the electrical characteristics of insulated gate transistors such as the MOS transistors, variability of gate electrode lengths caused by the optical proximity effect (OPE) and the loading effect should be eliminated. In Japanese Patent Laid-Open Publication No. Hei 10-200109, a method to reduce such variability of the gate electrode lengths by disposing dummy patterns around the gate electrode pattern in a photomask is proposed.
However, even though the variability of the gate electrode lengths is reduced at the mask level, the effective channel lengths of the transistors may vary dependent on the surface area of the impurity region formed by the ion implantation process, since such effective channel lengths depend on the diffusion of the dopants by the annealing process. Such effective channel length variability leads the electrical characteristics per unit channel length to unevenness. When the number of the doped dopants and the number of point defects in the impurity regions are varied dependent on the surface area of the impurity regions, such effective channel length variability generates. In addition, when the decay time of the point defects are affected by the volume restriction of the impurity region surrounded by a trench isolation region, the diffusion of the doped dopants by the annealing process becomes uneven in the semiconductor substrate.